View AUIRS2332JTR_9097928.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

september 3rd, 2012 automotive grade auirs2332j 3 - phase bridge driver ic features ? floating channel designed for bootstrap operation ? fully operational to +600 v ? tolerant to negative transient voltage C dv/dt immu ne ? gate drive supply range from 10 v to 20 v ? undervoltage lockout for all channels ? over-current shutdown turns off all six drivers ? independent half-bridge drivers ? matched propagation delay for all channels ? 3.3 v logic compatible ? outputs out of phase with inputs ? cross-conduction prevention logic ? integrated operational amplifier ? rohs compliant ? automotive qualified* typical applications ? automotive body electronics ? 3 phase motor control ? pumps and fans product summary v offset 600v v out 10 C 20v i o+ & i o- (typical) 250ma & 500ma t on & t off (typical) 540ns deadtime (typical) 850ns package options 44-lead plcc w/o 12 leads typical connection diagram downloaded from: http:///
auirs2332j 2 table of contents page description 3 qualification information 4 absolute maximum ratings 5 recommended operating conditions 6 dynamic electrical characteristics 6 static electrical characteristics 7 - 8 functional block diagram 8 input/output pin equivalent circuit diagram 9 lead definitions 10 lead assignments 10 application information and additional details 11 - 25 parameter temperature trends 26 - 29 package details 30 - 31 part marking information 32 ordering information 32 important notice 33 downloaded from: http:///
auirs2332j 3 description the auirs2332j is a high voltage, high speed power mosfet and igbt driver with three independent high and low side referenced output channels. proprietary hvic techno logy enables ruggedized monolithic construction. lo gic inputs are compatible with cmos or lsttl outputs, down to 3.3v logic. a ground-referenced operational amplifier p rovides analog feedback of bridge current via an external current sense resistor. a current trip function which term inates all six outputs is also derived from this resistor. an open drain faul t signal indicates if an over-current or undervolta ge shutdown has occurred. the output drivers feature a high pulse c urrent buffer stage designed for minimum driver cro ss-conduction. propagation delays are matched to simplify use at h igh frequencies. the floating channel can be used t o drive n-channel power mosfet or igbt in the high side configuration which operates up to 600 volts. downloaded from: http:///
auirs2332j 4 qualification information ? qualification level automotive (per aec - q100 ?? ) comments: this family of ics has passed an automoti ve qualification. irs industrial and consumer qualif ication level is granted by extension of the higher automot ive level. moisture sensitivity level msl3 ??? 245c (per ipc/jedec j-std-020) esd machine model class m2 (pass +/-200v) (per aec-q100-003) human body model class h1c (pass +/-1500v) ( per aec - q100 - 002 ) charged device model class c4 (+/-1000v) (per aec-q100-011) ic latch-up test class ii, level a (per aec-q100-004) rohs compliant yes ? qualification standards can be found at internation al rectifiers web site http://www.irf.com/ ?? exceptions (if any) to aec - q10 0 requirements are noted in the qualification report. ??? higher msl ratings may be available for the specifi c package types listed here. please contact your international rectifier sales representative for fu rther information. downloaded from: http:///
auirs2332j 5 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which permanent damage to the device may occ ur. these are stress ratings only, functional operation of the device at these or any other condition beyo nd those indicated in the recommended operating condition is not implied. exposure to absolute maximum-rated conditions for extended periods may affect device r eliability. all voltage parameters are absolute vol tages referenced to v so unless otherwise stated in the table. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditio ns. symbol definition min. max. units v b1,2,3 high side floating supply voltage -0.3 620 v v s1,2,3 high side floating offset voltage v b1,2,3 - 20 v b1,2,3 + 0.3 v ho1,2,3 high side floating output voltage v s1,2,3 - 0.3 v b1,2,3 + 0.3 v cc low side and logic fixed supply voltage -0.3 20 v ss logic ground v cc - 20 v cc + 0.3 v lo1,2,3 low side output voltage -0.3 v cc + 0.3 v in _______ ___ ___ logic input voltage ( hin1,2,3, lin1,2,3 & itr ip) v ss -0.3 (v ss + 15) or (v cc + 0.3) whichever is lower v flt fault output voltage v ss -0.3 v cc +0.3 v cao operational amplifier output voltage v ss -0.3 v cc +0.3 v ca- operational amplifier inverting input voltage v ss -0.3 v cc +0.3 dv s /dt allowable offset supply voltage transient 50 v/ns p d package power dissipation @ ta +25 c 2.0 w rth ja thermal resistance, junction to ambient 63 c/w rth jc thermal resistance, junction to case --- 21.95 c/ w t j junction temperature 150 c t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) 300 downloaded from: http:///
auirs2332j 6 recommended operating conditions the input/output logic timing diagram is shown in f igure 1. for proper operation the device should be used within the recommended conditions. all voltage parameters are absolute voltage referenced to v so. the v s offset rating is tested with all supplies biased at 15v differential . note 1: logic operational for v s of (v so -8 v) to (v so +600 v). logic state held for v s of (v so -8 v) to (v so C v bs ) . note 2: operational for transient negative vs of vss - 50 v with a 50 ns pulse width. guaranteed by design. r efer to the application information section of this data sheet for more details. note 3: cao input pin is internally clamped with a 5.2 v z ener diode. dynamic electrical characteristics unless otherwise noted, these specifications apply for an operating junction temperature range of -40 c tj 125c with bias conditions v bias (v cc , v bs1,2,3 ) = 15 v, c l = 1000 pf. symbol definition min typ max units test conditions t on turn-on propagation delay 400 540 700 ns v s1,2,3 = 0 v to 600 v t off turn-off propagation delay 400 540 700 t r turn-on rise time 80 145 v s1,2,3 = 0 v t f turn-off fall time 40 55 t itrip itrip to output shutdown propagation delay 400 625 920 t bl itrip blanking time 400 t flt itrip to fault indication delay 350 550 870 t flt, in input filter time (all six inputs) 325 t fltclr lin1,2,3 to fault clear time 5300 8500 13700 dt deadtime: 500 850 1100 v in = 0 v & 5 v without external deadtime mdt deadtime matching: 145 mt delay matching time (t on , t off ) 50 v in = 0 v & 5 v without external deadtime larger than dt pm pulse width distortion 75 pm input 10 s sr+ operational amplifier slew rate (+) 5 10 v/s 1 v input step sr- operational amplifier slew rate (-) 2.4 3.2 1 v input step symbol definition min. max. units v b1,2,3 high side floating supply voltage v s1,2,3 +10 v s1,2,3 +20 v v s1,2,3 static high side floating offset voltage v so -8 (note1) 600 v st1,2,3 transient high side floating offset voltage -50 (note2) 600 v ho1,2,3 high side floating output voltage v s1,2,3 v b1,2,3 v cc low side and logic fixed supply voltage 10 20 v ss logic ground -5 5 v lo1,2,3 low side output voltage 0 v cc v in logic input voltage (hin1,2,3, lin1,2,3 & itr ip) v ss v ss + 5 v flt fault output voltage v ss v cc v cao operational amplifier output voltage v ss v ss + 5 v ca- operational amplifier inverting input voltage v ss v ss + 5 t a ambient temperature -40 125 c downloaded from: http:///
auirs2332j 7 note: for high side pwm, hin pulse width must be > 1.5 u sec static electrical characteristics unless otherwise noted, these specifications apply for an operating junction temperature range of -40 c tj 125c with bias conditions of v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss . the v in, v th and i in parameters are referenced to v ss and are applicable to all six logic input leads: hi n1,2,3 & lin1,2,3. the v o and i o parameters are referenced to v so1,2,3 and are applicable to the respective output leads: ho1,2,3 or lo1,2,3. symbol definition min typ max units test conditions v ih logic 0 input voltage (out = lo) 2.2 v v il logic 1 input voltage (out = hi) 0.8 v it,th+ itrip input positive going threshold 400 490 580 mv v oh high level output voltage, v bias - v o 1150 v in = 0 v, i o = 20 ma v ol low level output voltage, v o 400 v in = 5 v, i o = 20 ma i lk offset supply leakage current 50 a v b = v s = 600 v i qbs quiescent v bs supply current 37 50 v in = 0 v or 4 v i qcc quiescent v cc supply current 4.5 6.2 ma v in = 0 v i in+ logic 1 input bias current (out =hi) -450 -300 -100 a v in = 0 v i in - logic 0 input bias current (out = lo) - 3 5 0 - 220 - 100 v in = 4 v i itrip+ high itrip bias current 5 10 itrip = 4 v i itrip - low itrip bias current 30 na itrip = 0 v v bsuv+ v bs supply undervoltage positive going threshold 7.5 8.3 9.2 v v bsuv- v bs supply undervoltage negative going threshold 7.1 7.9 8.8 v ccuv+ v cc supply undervoltage positive going threshold 8.3 8.9 9.7 v ccuv- v cc supply undervoltage negative going threshold 8 8.6 9.4 v ccuvh hysteresis 0.3 v bsuvh hysteresis 0.4 r on, flt fault low on-resistance 55 75 ? i o+ output high short circuit pulsed current -250 -180 ma v o = 0 v, v in = 0 v pw 10 us i o- output low short circuit pulsed current 375 500 v o = 15 v, v in = 5 v pw 10 us v os operational amplifier input offset voltage 20 mv v so = 0.2 v i ca - ca- input bias current 100 na v ca - = 1 v cmrr operational amplifier common mode rejection ratio 80 db v so = 0.1 v & 5 v psrr operational amplifier power supply rejection ratio 75 v so = 0.2 v v cc = 9.7 v & 20 v v oh,amp operational amplifier high level output voltage 4.8 5.2 5.6 v v ca- = 0 v, v so =1 v v ol,amp operational amplifier low level output voltage 40 mv v ca- = 1 v, v so =0 v i src,amp operational amplifier output source current -7 - 4 ma v ca- = 0 v, v so =1 v v cao = 4 v i snk,amp operational amplifier output sink current 1 2.1 v ca- = 1 v, v so =0 v v cao = 2 v downloaded from: http:///
auirs2332j 8 i o+,amp operational amplifier output high short circuit current -30 -10 v ca- = 0 v, v so =5 v v cao = 0 v i o-,amp operational amplifier output low short circuit current 4 v ca- = 5 v, v so =0 v v cao = 5 v functional block diagram downloaded from: http:///
auirs2332j 9 input/output pin equivalent circuit diagram : v ss v cc 5v esd diode esd diode 250 ohm 50 kohm 20v hin 123 , lin 123 v ss v cc 5v esd diode esd diode 250 ohm itrip 1 mohm downloaded from: http:///
auirs2332j 10 20v v b123 v s123 ho 123 esd diode esd diode downloaded from: http:///
auirs2332j 11 lead definitions symbol description hin1,2,3 logic input for high side gate driver outputs (ho1, 2,3), out of phase lin1,2,3 logic input for low side gate driver output (lo1,2, 3), out of phase fault indicates over-current or undervoltage lockout (low side) has occurred, negative logic v cc low side and logic fixed supply itrip input for over-current shutdown cao output of current amplifier ca- negative input of current amplifier v ss logic ground v b1,2,3 high side floating supply ho1,2,3 high side gate drive output v s1,2,3 high side floating supply return lo1,2,3 low side gate drive output v so low side return and positive input of current ampl ifier #leas7, #11, #13, #15, #17, #20, #21 are n.c. lead assignments leads num. 7, 11, 13, 15, 17, 20 and 21 are n.c. downloaded from: http:///
auirs2332j 12 application information and additional details information regarding the following topics are incl uded as subsections within this section of the data sheet. ? igbt/mosfet gate drive ? switching and timing relationships ? deadtime ? matched propagation delays ? input logic compatibility ? undervoltage lockout protection ? shoot-through protection ? fault reporting ? over-current protection ? over-temperature shutdown protection ? truth table: undervoltage lockout, itrip ? advanced input filter ? short-pulse / noise rejection ? integrated bootstrap functionality ? bootstrap power supply design ? separate logic and power grounds ? negative v s transient soa ? dc- bus current sensing ? pcb layout tips ? additional documentation igbt/mosfet gate drive the auirs2332j hvic is designed to drive up to six mosfet or igbt power devices. figures 1 and 2 illu strate several parameters associated with the gate drive functiona lity of the hvic. the output current of the hvic, used to drive the gate of the power switch, is defined as i o . the voltage that drives the gate of the external power switch is defined as v ho for the high-side power switch and v lo for the low-side power switch; this parameter is s ometimes generically called v out and in this case does not differentiate between the high-side o r low-side output voltage. v s (or com) ho (or lo) v b (or v cc ) i o+ v ho (or v lo ) + - v s (or com) ho (or lo) v b (or v cc ) i o- figure 1: hvic sourcing current figure 2: hvic sinking current downloaded from: http:///
auirs2332j 13 switching and timing relationships the relationship between the input and output signa ls of the auirs2332j are illustrated below in figur es 3. from these figures, we can see the definitions of several timi ng parameters (i.e., pw in , pw out , t on , t off , t r , and t f ) associated with this device. linx (or hinx) 50% 50% pw in pw out 10% 10% 90% 90% t off t on t r t f lox (or hox) figure 3: switching time waveforms the following two figures illustrate the timing rel ationships of some of the functionalities of the au irs2332j. these functionalities are described in further detail lat er in this document. during interval a of figure 4, the hvic has receive d the command to turn-on both the high- and low-sid e switches at the same time; as a result, the shoot-through protectio n of the hvic has prevented this condition and both the high- and low-side output are held in the off state. interval b of figures 4 shows that the signal on th e itrip input pin has gone from a low to a high sta te; as a result, all of the gate drive outputs have been disabled (i.e., see th at hox has returned to the low state; lox is also h eld low) and a fault is reported by the fault output transitioning to the l ow state. once the itrip input has returned to the low state, the fault condition is latched until the all linx become high . hin1,2,3 lin1, 2, 3 fault itrip ho1, 2, 3 lo1,2, 3 a b figure 4: input/output timing diagram downloaded from: http:///
auirs2332j 14 deadtime this hvic features integrated deadtime protection c ircuitry. the deadtime for this ic is fixed; other ics within irs hvic portfolio feature programmable deadtime for greater design flexibility. the deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side powe r switches are held off; this is done to ensure tha t the power switch being turned off has fully turned off before the second p ower switch is turned on. this minimum deadtime is automatically inserted whenever the external deadtime is shorter than dt; external deadtimes larger than dt are not modified by the gate driver. figure 5 illustrates the deadtime period and the re lationship between the output gate signals. the deadtime circuitry of the auirs2332j is matched with respect to the high- and low-side outputs of a given channel; additionally, the deadtimes of each of the three ch annels are matched. figure 5 : illustration of deadtime matched propagation delays the auirs2332j hvic is designed with propagation de lay matching circuitry. with this feature, the ic s response at the output to a signal at the input requires approximat ely the same time duration (i.e., t on , t off ) for both the low-side channels and the high-side channels. additionally, the propagat ion delay for each low-side channel is matched when compared to the other low-side channels and the propagation delays of the high-side channels are matched with each oth er. the propagation turn-on delay (t on ) of the auirs2332j is matched to the propagation t urn-on delay (t off ). input logic compatibility the inputs of this ic are compatible with standard cmos and ttl outputs. the auirs2332j has been desi gned to be compatible with 3.3 v and 5 v logic-level signals. the auirs2332j features an integrated 5.2 v zener clamp on the hin, lin, and itrip pins. figure 6 illustrates an input signal to the auirs2332j, its input threshold valu es, and the logic state of the ic as a result of the input signal. downloaded from: http:///
auirs2332j 15 figure 6 : hin & lin input thresholds undervoltage lockout protection this ic provides undervoltage lockout protection on both the v cc (logic and low-side circuitry) power supply and th e v bs (high-side circuitry) power supply. figure 7 is us ed to illustrate this concept; v cc (or v bs ) is plotted over time and as the waveform crosses the uvlo threshold (v ccuv+/- or v bsuv+/- ) the undervoltage protection is enabled or disable d. upon power-up, should the v cc voltage fail to reach the v ccuv+ threshold, the ic will not turn-on. additionally, if the v cc voltage decreases below the v ccuv- threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the fault pin will transition to the low state to inform the controller of the fault condition. upon power-up, should the v bs voltage fail to reach the v bsuv threshold, the ic will not turn-on. additionally, if the v bs voltage decreases below the v bsuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the ic . the uvlo protection ensures that the ic drives the external power devices only when the gate supply vo ltage is sufficient to fully enhance the power devices. without this feat ure, the gates of the external power switch could b e driven with a low voltage, resulting in the power switch conducting c urrent while the channel impedance is high; this co uld result in very high conduction losses within the power device and could lead to power device failure. figure 7: uvlo protection shoot-through protection downloaded from: http:///
auirs2332j 16 the auirs2332j is equipped with shoot-through prote ction circuitry (also known as cross-conduction pre vention circuitry). figure 8 shows how this protection circuitry preven ts both the high- and low-side switches from conduc ting at the same time. table 1 illustrates the input/output relationship o f the devices in the form of a truth table. note t hat the auirs2332j has inverting inputs (the output is out-of-phase with i ts respective input). figure 8 : illustration of shoot - through protec tion circuitry auirs2332j hin lin ho lo 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 table 1: input/output truth table fault reporting the auirs2332j provides an integrated fault reporti ng output. there are two situations that would cau se the hvic to report a fault via the fault pin. the first is an undervo ltage condition of v cc and the second is if the itrip pin recognizes a fau lt. once the fault condition occurs, the fault pin is i nternally pulled to v ss and the fault condition is latched. the fault outp ut stays in the low state until the fault condition ha s been removed by all linx set to high state. once the fault is removed, the voltage on the fault pin will return to v cc . over-current protection the auirs2332j hvics are equipped with an itrip inp ut pin. this functionality can be used to detect o ver-current events in the dc- bus. once the hvic detects an over-current event through the itrip pin, the outputs are shutd own, a fault is reported through the fault pin. the level of current at which the over-current prot ection is initiated is determined by the resistor n etwork (i.e., r 0 , r 1 , and r 2 ) connected to itrip as shown in figure 9, and the it rip threshold (v it,th+ ). the circuit designer will need to determine the maximum allowable level of current in the dc- bus a nd select r 0 , r 1 , and r 2 such that the voltage at node v x reaches the over-current threshold (v it,th+ ) at that current level. v it,th+ = r 0 i dc- (r 1 /(r 1 +r 2 )) downloaded from: http:///
auirs2332j 17 v cc hin (x3) itrip v ss fault com lin (x 3 ) lo (x3) ho ( x3) v b (x3) v s (x3) r 1 au i rs 23 3 2 j r 2 r 0 i dc- figure 9: programming the over-current protection for example, a typical value for resistor r 0 could be 50 m ? . the voltage of the itrip pin should not be allow ed to exceed 5 v; if necessary, an external voltage clamp may be u sed. over-temperature shutdown protection the itrip input of the auirs2332j can also be used to detect over-temperature events in the system and initiate a shutdown of the hvic (and power switches) at that t ime. in order to use this functionality, the circu it designer will need to design the resistor network as shown in figure 10 a nd select the maximum allowable temperature. this network consists of a thermistor and two stand ard resistors r 3 and r 4 . as the temperature changes, the resistance of the thermistor will change; this will result in a c hange of voltage at node v x . the resistor values should be selected such the voltage v x should reach the threshold voltage (v it,th+ ) of the itrip functionality by the time that the m aximum allowable temperature is reached. the voltage of the itrip p in should not be allowed to exceed 5 v. when using both the over-current protection and ov er-temperature protection with the itrip input, or- ing diodes (e.g., dl4148) can be used. this network is shown in figu re 11; the or-ing diodes have been labeled d 1 and d 2 . figure 10: programming over-temperature protection figure 11: using over-current protection and over-t emperature protection truth table: undervoltage lockout and itrip downloaded from: http:///
auirs2332j 18 table 2 provides the truth table for the auirs2332j . the first line shows that the uvlo for v cc has been tripped; the fault output has gone low and the gate drive outputs have been disabled. v ccuv is not latched in this case and when v cc is greater than v ccuv , the fault output returns to the high impedance st ate. the second case shows that the uvlo for v bs has been tripped and that the high-side gate drive outputs have been disabled. after v bs exceeds the v bsuv threshold , ho will stay low until the hvic input receives a new falling transition of hin. the third case shows the normal operation of the hv ic. the fourth case illustrates that the itrip tri p threshold has been reached and that the gate drive outputs have been d isabled and a fault has been reported through the f ault pin. the fault output stays in the low state until the fault condi tion has been removed by all linx set to high state . once the fault is removed, the voltage on the fault pin will return t o v cc . vcc vbs itrip fault lo ho uvlo v cc < v ccuv --- --- 0 0 0 uvlo v bs 15 v < v bsuv 0 v high impedance lin 0 normal operation 15 v 15 v 0 v high impedance lin hin itrip fault 15 v 15 v >v itrip 0 0 0 table 2: auirs2332j uvlo, itrip & fault truth table advanced input filter the advanced input filter allows an improvement in the input/output pulse symmetry of the hvic and hel ps to reject noise spikes and short pulses. this input filter has bee n applied to the hin and lin. the working principle of the new filter is shown in figures 12 and 13. figure 12 shows a typical input filter and the asym metry of the input and output. the upper pair of w aveforms (example 1) shows an input signal with a duration much longer t hen t fil,in ; the resulting output is approximately the differe nce between the input signal and t fil,in . the lower pair of waveforms (example 2) show an input signal with a duration slightly longer then t fil,in ; the resulting output is approximately the differe nce between the input signal and t fil,in . figure 13 shows the advanced input filter and the s ymmetry between the input and output. the upper pa ir of waveforms (example 1) show an input signal with a duration mu ch longer then t fil,in ; the resulting output is approximately the same duration as the input signal. the lower pair of w aveforms (example 2) show an input signal with a du ration slightly longer then t fil,in ; the resulting output is approximately the same du ration as the input signal. figure 1 2 : typical input filter figure 1 3 : advanced input filter short-pulse / noise rejection downloaded from: http:///
auirs2332j 19 this devices input filter provides protection agai nst short-pulses (e.g., noise) on the input lines. if the duration of the input signal is less than t fil,in , the output will not change states. example 1 of figure 14 shows the input and output in the low sta te with positive noise spikes of durations less than t fil,in ; the output does not change states. example 2 of figure 19 shows the input and output in the high state with negative no ise spikes of durations less than t fil,in ; the output does not change states. example 1 example 2 figure 14: noise rejecting input filters figures 15 and 16 present lab data that illustrates the characteristics of the input filters while rec eiving on and off pulses. the input filter characteristic is shown in figure 15; the left side illustrates the narrow pulse on ( short positive pulse) characteristic while the left shows the narrow puls e off (short negative pulse) characteristic. the x -axis of figure 20 shows the duration of pw in , while the y-axis shows the resulting pw out duration. it can be seen that for a pw in duration less than t fil,in , that the resulting pw out duration is zero (e.g., the filter rejects the inp ut signal/noise). we also see that once the pw in duration exceed t fil,in , that the pw out durations mimic the pw in durations very well over this interval with the sy mmetry improving as the duration increases. to ensure pro per operation of the hvic, it is suggested that the input pulse width for the high-side inputs be 500 ns. the difference between the pw out and pw in signals of both the narrow on and narrow off cases is shown in figure 16; the careful reader will note the scale of the y-axi s. the x-axis of figure 21 shows the duration of p w in , while the y-axis shows the resulting pw out Cpw in duration. this data illustrates the performance a nd near symmetry of this input filter. time (ns) figure 15: auirs2332j input filter characteristic downloaded from: http:///
auirs2332j 20 figure 16 : difference between the input pulse and the output pulse separate logic and power grounds the auirs2332j has separate logic and power ground pin (v ss and vso respectively) to eliminate some of the noi se problems that can occur in power conversion applica tions. current sensing shunts are commonly used in many applications for power inverter protection (i.e., over-current p rotection), and in the case of motor drive applicat ions, for motor current measurements. in these situations, it is often ben eficial to separate the logic and power grounds. figure 19 shows a hvic with separate v ss and vso pins and how these two grounds are used in the system. the v ss is used as the reference point for the logic and over- current circuitry; v x in the figure is the voltage between the itrip pin and the v ss pin. alternatively, the vso pin is the reference point for the low-side gate drive circuitry. the o utput voltage used to drive the low-side gate is v lo -vso; the gate-emitter voltage (v ge ) of the low-side switch is the output voltage of t he driver minus the drop across r g,lo . v s (x3) hvic ho (x3) v b (x3) lo (x3) com dc+ bus dc- bus v cc d bs c bs v ss r g,lo r g,ho v s1 v s2 v s3 r 1 r 2 r 0 v ge1 + - v ge2 + - v ge3 + - itrip v x + - figure 19 : separate v ss and vso (com) pins negative v s transient soa downloaded from: http:///
auirs2332j 21 a common problem in todays high-power switching co nverters is the transient response of the switch no des voltage as the power switches transition on and off quickly while carrying a large current. a typical 3-phase invert er circuit is shown in figure 20; here we define the power switches and di odes of the inverter. if the high-side switch (e.g., the igbt q1 in figur es 21 and 22) switches off, while the u phase curre nt is flowing to an inductive load, a current commutation occurs from h igh-side switch (q1) to the diode (d2) in parallel with the low-side switch of the same inverter leg. at the same instance, th e voltage node v s1 , swings from the positive dc bus voltage to the ne gative dc bus voltage. figure 20: three phase inverter q1 on d2 v s1 q2 off i u dc+ bus dc- bus figure 2 1 : q1 conducting figure 2 2 : d2 conducting also when the v phase current flows from the induct ive load back to the inverter (see figures 23 and 2 4), and q4 igbt switches on, the current commutation occurs from d3 to q4. at the same instance, the voltage node, v s2 , swings from the positive dc bus voltage to the negative dc bus volt age. downloaded from: http:///
auirs2332j 22 figure 2 3 : d3 conducting figure 2 4 : q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the ne gative dc bus, rather it swings below the level of the negative dc bus. this unders hoot voltage is called negative v s transient. the circuit shown in figure 25 depicts one leg of t he three phase inverter; figures 26 and 27 show a s implified illustration of the commutation of the current between q1 and d2. t he parasitic inductances in the power circuit from the die bonding to the pcb tracks are lumped together in l c and l e for each igbt. when the high-side switch is on, v s1 is below the dc+ voltage by the voltage drops associated with the power swit ch and the parasitic elements of the circuit. when the high-side power switch turns off, the load current momentarily flow s in the low-side freewheeling diode due to the ind uctive load connected to v s1 (the load is not shown in these figures). this cu rrent flows from the dc- bus (which is connected to the vso pin of the hvic) to the load and a negative voltage between v s1 and the dc- bus is induced (i.e., the vso pin of t he hvic is at a higher potential than the v s pin). figure 25 : parasitic elements figure 26 : v s positive figure 27 : v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 3-5 v/ns. the negat ive v s transient voltage can exceed this range during some events such as sh ort circuit and over-current shutdown, when di/dt i s greater than in normal operation. international rectifiers hvics have been designed for the robustness required in many of todays dema nding applications. an indication of the auirs2332js robustness can be seen in figure 28, where there is represented the auirs2332j safe operating area at v bs =15v based on repetitive negative v s spikes. a negative v s transient voltage falling in the grey area (outside soa) may lead to ic permanent damage; vice versa unwanted functional anomalies or permanent da mage to the ic do not appear if negative vs transients fall inside soa. at v bs =15v in case of -v s transients greater than -16.5 v for a period of ti me greater than 50 ns; the hvic will hold by design the high-side outputs in the off state for 4.5 s. downloaded from: http:///
auirs2332j 23 f igure 28 : negative v s transient soa for auirs2332j even though the auirs2332j has been shown able to h andle these large negative v s transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layo ut and component use. dc- bus current sensing a ground referenced current signal amplifier has be en included so that the current in the return leg o f the dc bus may be monitored. a typical circuit configuration is provi ded in fig.29. the signal coming from the shunt res istor is amplified by the ratio (r1+r2)/r2. additional details can be found o n design tip dt 92-6. this design tip is available at www.irf.com . figure 29 : current amplifier typical configuration in the following figures 30, 31, 32, 33 the configu rations used to measure the operational amplifier c haracteristics are shown. downloaded from: http:///
auirs2332j 24 v cc cao v so ca- v ss 15 v 50 pf 1 v 0v 90% 10% 1v 0v t1 t2 v t1 v sr + t2 v sr - figure 30: operational amplifier slew rate measurem ent figure 31: operational amplifier input offset v oltage measurement v cc cao v so ca - v ss 15v measure v cao 1 at v so = 0.1v v cao2 at v so = 1.1v cmrr = -20 * log (v cao1 C0.1v) C(v cao 2 C1.1v) 1v (db) figure 32: operational amplifier common mode reject ion measurement figure 33: operational amplifier power supply rejec tion measurement pcb layout tips distance between high and low voltage components: its strongly recommended to place the components t ied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. the auirs2332j in the plcc44 package has had some unused pins removed in order to maximi ze the distance between the high voltage and low vo ltage pins. please see the case outline plcc44 information in t his datasheet for the details. ground plane: in order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antenna s and are able to receive and transmit em noise (se e figure 34). in order to reduce the em coupling and improve the pow er switch turn on/off performance, the gate drive l oops must be reduced as much as possible. moreover, current can be injec ted inside the gate drive loop via the igbt collect or-to-gate parasitic downloaded from: http:///
auirs2332j 25 capacitance. the parasitic auto-inductance of the g ate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect . figure 34 : antenna loops supply capacitor: it is recommended to place a byp ass capacitor (c in ) between the v cc and v ss pins. this connection is shown in figure 35. a ceramic 1 f ceramic capacitor is suitable for most applicatio ns. this component should be placed as close as possible to the pins in order to reduce pa rasitic elements. v cc hin (x3) itrip v ss fault com lin (x 3 ) lo (x3) ho ( x3) v b (x3) v s (x3) r 1 r 2 r 0 i dc- figure 35: supply capacitor routing and placement: power stage pcb parasitic el ements can contribute to large negative voltage tra nsients at the switch node; it is recommended to limit the phase voltage negative transients. in order to avoid such condit ions, it is recommended to 1) minimize the high-side emitter to low-side co llector distance, and 2) minimize the low-side emit ter to negative bus rail stray inductance. however, where negative v s spikes remain excessive, further steps may be take n to reduce the spike. this includes placing a resistor (5 ? or less) between the v s pin and the switch node (see figure 36), and in so me cases using a clamping diode between v ss and v s (see figure 37). see dt04-4 at www.irf.com for more detailed information. downloaded from: http:///
auirs2332j 26 figure 3 6 : v s resistor figure 3 7 : v s clamping diode additional documentation several technical documents related to the use of h vics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these documents. dt97-3: managing transients in control ic driven po wer stages an-1123: bootstrap network analysis: focusing on th e integrated bootstrap functionality dt04-4: using monolithic high voltage gate drivers an-978: hv floating mos-gate driver ics downloaded from: http:///
auirs2332j 27 parameter temperature trends figures illustrated in this chapter provide informa tion on the experimental performance of the auirs23 32j hvic. the line plotted in each figure is generated from actual lab data. a large number of individual samples were tested at three temperatures (-40 oc, 25 oc, a nd 125 oc) in order to generate the experimental cu rve. the line consists of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. the i ndividual data points on the typ. curve were determ ined by calculating the averaged experimental value of the parameter (for a given temperature). figure 38. turn-on propagation delay vs. temperatur e figure 39. turn-off propagation delay vs. temperatu re figure 40. turn-on rise time vs. temperature figure 41. turn-off fall time vs. temperature downloaded from: http:///
auirs2332j 28 figure 42. itrip to output shutdown propagation del ay vs. temperature figure 43. itrip to fault indication delay vs. temperature figure 44. dead time vs. temperature figure 45. offset supply leakage current vs. temper ature figure 46. quiescent v cc supply current vs. temperature figure 47. quiescent v bs supply current vs. temperature downloaded from: http:///
auirs2332j 29 figure 48. high level output voltage vs. temperatur e figure 49. low level output voltage vs. temperature figure 50. v cc supply undervoltage positive going threshold vs. temperature figure 51. v cc supply undervoltage negative going threshold vs. temperature figure 52. v bs supply undervoltage positive going threshold vs. temperature figure 53. v bs supply undervoltage negative going threshold vs. temperature downloaded from: http:///
auirs2332j 30 figure 54. itrip input positive going threshold vs. temperature figure 55. op-amp input offset voltage vs. temperat ure figure 56. op - amp high level output voltage vs. temperature downloaded from: http:///
auirs2332j 31 case outlines downloaded from: http:///
auirs2332j 32 package land pattern downloaded from: http:///
auirs2332j 33 tape and reel details: plcc44 carrier tape dimension for 44plcc code min max min max a 23.90 24.10 0.94 0.948 b 3.90 4.10 0.153 0.161 c 31.70 32.30 1.248 1.271 d 14.10 14.30 0.555 0.562 e 17.90 18.10 0.704 0.712 f 17.90 18.10 0.704 0.712 g 2.00 n/a 0.078 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 44plcc code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 38.4 n/a 1.511 g 34.7 35.8 1.366 1.409 h 32.6 33.1 1.283 1.303 metric imperial e f a c d g a b h note : controlling dim ension in m m loaded tape feed direction a h f e g d b c downloaded from: http:///
auirs2332j 34 part marking information ordering information base part number package type standard pack complete part number form quantity auirs2332j plcc44 tube/bulk 27 auirs2332j tape and reel 500 AUIRS2332JTR downloaded from: http:///
auirs2332j 35 important notice unless specifically designated for the automotive m arket, international rectifier corporation and its subsidiaries (ir) reserve the right to make correct ions, modifications, enhancements, improvements, an d other changes to its products and services at any time an d to discontinue any product or services without no tice. part numbers designated with the au prefix follow auto motive industry and / or customer specific requirem ents with regards to product discontinuance and process change notification. all products are sold subject to irs terms and conditions of sale supplied at the time o f order acknowledgment. ir warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with irs standard warranty. testing an d other quality control techniques are used to the extent ir deems necessary to support this warranty. except wh ere mandated by government requirements, testing of all parameters of each product is not necessarily perfo rmed. ir assumes no liability for applications assistance or customer product design. customers are responsi ble for their products and applications using ir components . to minimize the risks with customer products and applications, customers should provide adequate des ign and operating safeguards. reproduction of ir information in ir data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated war ranties, conditions, limitations, and notices. rep roduction of this information with alterations is an unfair a nd deceptive business practice. ir is not responsi ble or liable for such altered documentation. information of thi rd parties may be subject to additional restriction s. resale of ir products or serviced with statements d ifferent from or beyond the parameters stated by ir for that product or service voids all express and any implie d warranties for the associated ir product or servi ce and is an unfair and deceptive business practice. ir is n ot responsible or liable for any such statements. ir products are not designed, intended, or authoriz ed for use as components in systems intended for su rgical implant into the body, or in other applications int ended to support or sustain life, or in any other a pplication in which the failure of the ir product could create a situation where personal injury or death may occur. should buyer purchase or use ir products for any such unin tended or unauthorized application, buyer shall ind emnify and hold international rectifier and its officers, employees, subsidiaries, affiliates, and distributo rs harmless against all claims, costs, damages, and expenses, a nd reasonable attorney fees arising out of, directl y or indirectly, any claim of personal injury or death a ssociated with such unintended or unauthorized use, even if such claim alleges that ir was negligent regarding the design or manufacture of the product. only products certified as military grade by the de fense logistics agency (dla) of the us department o f defense, are designed and manufactured to meet dla military specifications required by certain militar y, aerospace or other applications. buyers acknowledge and agree that any use of ir products not certifie d by dla as military-grade, in applications requiring mi litary grade products, is solely at the buyers own risk and that they are solely responsible for compliance wit h all legal and regulatory requirements in connecti on with such use. ir products are neither designed nor intended for u se in automotive applications or environments unles s the specific ir products are designated by ir as compli ant with iso/ts 16949 requirements and bear a part number including the designation au. buyers ackn owledge and agree that, if they use any non-designa ted products in automotive applications, ir will not be responsible for any failure to meet such requireme nts. for technical support, please contact irs technica l assistance center http://www.irf.com/technical-info/ world headquarters: 101 n. sepulveda blvd., el segundo, california 9024 5 tel: (310) 252-7105 downloaded from: http:///
* qualification standards can be found on irs web site www.irf.com ? 2010 international rectifier revision history date comment jul. 7, 2010 converted from industrial datasheet july 28, 2010 typ application section updated in front page. logic block diagram modified because uvvcc is not l atched. added input output equivalent circuit diagram may 6, 2011 added tri-temp graphs; updated qual inf o page and table of contents. formated to au ds for mat may 11, 2011 ton and toff typ values changed from 500ns to 540n s.tf typ from 35ns to 40ns dt typ from 700ns to 850ns.iqbs typ from 30ua to 37 ua; iqcc typ from 4.0ua to 4.5ua. itrip to output shutdown propagation delay typ fro m 660ns to 625ns. voh max from 1v to 1.1v. vccuv+ typ from 9v to 8.9v; vccuv- from 8.7v to 8. 6v. vbsuv+ typ from 8.35v to 8.3v; vccuv- from 7.95v to 7.9v. may 11, 2011 iin+ min changed from -400 to -450; iin- min change d from -300 to -350; io- min changed from 420 to 375; tr max changed from 125 to 145; mdt max change from 140 to 145; voh max changed from 1.1 to 1.15. may 13, 2011 changed formula in figure 31 may 17, 2011 updated cdm class june 7, 2011 added rth jc june 24, 2011 updated disclaimer august 30 th , 2012 updated case outline (more readable) and added pack age land pattern september, 3 rd , 2012 added nc (not connected) in lead assignment figure and text. package land pattern updated downloaded from: http:///

▲Up To Search▲

Price & Availability of AUIRS2332JTR

	To Download AUIRS2332JTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .